HIPERFIT

February Seminar

The HIPERFIT February 2013 seminar is planned for Tuesday, February 5 from 15:00 to 16:30 at the DIKU small auditorium (Lille Aud), where Andreas Magnussen from Velocytech is giving a talk:

  • 15:00-16:00. FPGA technology for High performance computing with low latency (Andreas Magnussen, CTO, Velocytech).

  • 16:00-16:30. A light refreshment, served by HIPERFIT.

More information about the talk is given below.

We look forward to see you at the seminar!

Best Regards,

Martin Elsman

HIPERFIT Center Manager

FPGA technology for High performance computing with low latency

Andreas Magnussen, Velocytech

15:00-16:00 February 5, 2013

The (DIKU) small auditorium at Universitetsparken 1 (UP1)

Velocytech develops IP for high speed communication and connectivity in FPGA and ASIC. The FPGA sizes follows Mores law. The FPGA can be used to implement high performance computation logic and high speed and low latency communication. This opens up for a number of new applications which require high network performance.

The presentation will give an overview of the type of problems that can be addressed in FPGA systems today and what network and system performance improvements that can be achieved. We will also discuss design and test issues that relates to FPGA development.

Scientific host: Brian Vinter, HIPERFIT

Andreas Magnussen has 30 years of professional international working experience in the electronic industry (data communication and telecommunication), where he has held senior positions within engineering (hardware, software, ASIC and systems), marketing and management.

Education:

  • E.E. (elektronik mekaniker) in 1984 from Brüel & Kjær A/S.
  • M.Sc. E.E. (civilingeniør) in 1991 from DTU, Technical University of Denmark.
  • Ph.D. in 1997 from DTU (ATM switching system).
  • Executive MBA (MMT) in 2005 from DTU&TEM.

Key experience and credentials:

Tele and data networks, software systems, communication protocols, communication components, system design, marketing and management. Architecture, design, implemented and tested state of the art ATM layer chip 155Mbps with integrated switching and line functions (1995). Completed a high number of complex system designs in tele and data communications. Re-defined ASIC strategy and ASIC team rebuilding at Intel (2001). CEO at IPBlaze (2001). CTO at Velocytech (2012).

  • Brüel & Kjær (1982-1991)
  • DTU (1991-1992)
  • NKT Elektronik/DSC/Tellabs (1992-2000)
  • Intel (2000-2001)
  • IPBlaze A/S (2001-2011)
  • Velocytech APS (2012-now)

Published

30 January 2013

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